EDN

Establishing timing correlation between tools

In a SoC physical design flow, it is very important that there is correlation with respect to timing between various tools. Perfect timing correlation between tools leads to faster timing closure, and ...
EDN

Trip points for IC-timing analysis

If you are a budding timing-analysis engineer or even a veteran, understanding trip points, which all major timing-analysis tools incorporate, is essential. Engineers use trip points in ...
Design-Reuse

Cadence Timing Signoff Tools Enable MaxLinear to Deliver Industry's First 400Gbps PAM4 SoC on 16FF Process

SAN JOSE, Calif. -- 10 Dec 2018 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that MaxLinear, Inc., used Cadence ® timing signoff tools to successfully deliver the MxL935xx Telluride ...
Electronic Design

Oh, The Pain (Of Timing Closure At 28 nm)

What to do, what to do? Chip complexity continues to grow and design schedules are more aggressive, yet design teams are staying the same size or even being scaled back. Something has to give. A key ...